Electronic equipment, such as televisions, telephones, radios, and computers, is constructed using semiconductor microprocessors, integrated circuits, memory chips, and the like. These semiconductor components are typically fabricated on a semiconductor substrate and are constructed using various microelectronic devices such as transistors, capacitors, diodes, resistors, and so forth. Each microelectronic device is typically a pattern of conductor, semiconductor, and insulator regions formed on the semiconductor substrate.
Conventional semiconductor memory devices fall into two general classes: volatile memories and non-volatile memories. Volatile memories are generally faster and less expensive, but lose (or “forget”) their data when the power is turned off. Non-volatile memories, while slower and more expensive to fabricate, have the advantage that they retain their data even during long periods when no power is available. Non-volatile semiconductor memory devices include read-only-memory (“ROM”) devices, programmable-read-only-memory (“PROM”) devices, erasable-programmable-read-only-memory (“EPROM”) devices and electrically-erasable-programmable-read-only-memory (“EEPROM”) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Flash memory is formed from an array of memory cells. Data can be written to each cell within the array, but, as indicated, the data is erased in blocks of cells. Each cell is a floating gate transistor having a source, a drain, a floating gate, and a control gate. The floating gate and the control gate are typically fabricated from polycrystalline silicon doped with an appropriate doping material (e.g., phosphorous) to make the polycrystalline silicon conductive. The floating gate is isolated electrically, and is separated from a substrate region by a gate dielectric or tunnel dielectric layer of insulating material. The floating gate and control gate are typically separated from each other by a layer of insulating material. The substrate region includes source/drain regions defining a channel region therebetween. To store and erase data, the floating gate uses channel hot electrons for writing from the transistor's drain, and uses Fowler-Nordheim tunneling for erasure from the transistor's source.
An integrated circuit includes a large number of closely spaced semiconductor devices formed on a semiconductor substrate. Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times, and reducing cell dimensions. With the continuing miniaturization of integrated circuits, there is a relentless need to continually reduce the size of the memory array or, alternately, to increase the density of the memory array. A major goal in the semiconductor industry has been to reduce device size and spacing to achieve denser and denser packing, and to reduce the consumption of valuable space.
The density of the microelectronic devices on the semiconductor substrate may be increased by decreasing spacing between each of the various semiconductor devices. The decrease in spacing allows a larger number of such microelectronic devices to be formed on the semiconductor substrate. As a result, the computing power and speed of the semiconductor component may be greatly improved. The continuing reduction of design features, however, generates numerous problems challenging the limitations of conventional semiconductor technology.
One challenge in miniaturization is presented by the so-called “isolation structures” that are necessary to prevent each memory cell from interfering with the operation of its neighbors. Floating gate transistors are electrically isolated from one another by such isolation structures. One type of isolation structure that is used is a LOCal Oxidation of Silicon (“LOCOS”) structure. LOCOS structures are generally formed by thermally growing a localized oxidation layer between the cells to electrically isolate the cells. One problem with the LOCOS structure is that the structure includes non-functional areas that waste valuable space on the semiconductor substrate, interfering with the need to achieve denser and denser packing.
Another type of isolation structure used is a Shallow Trench Isolation (“STI”). STI structures are generally formed by etching a trench between the cells and filling the trench with a suitable dielectric (insulating) material. STI structures are smaller than LOCOS structures and allow the memory cells to be spaced closer together to increase the density of cells in the array. However, STI structures are often not used in flash memory due to the difficulty in forming the source line that connects the cells in each row. The source line in flash memory utilizing STI structures often has a higher resistance than a corresponding flash memory that uses LOCOS structures. The increased electrical resistance reduces the operational performance of the memory.
Another miniaturization challenge has to do with how the various circuit elements are connected to each other in a semiconductor device. A flash EEPROM chip or die is commonly-formed with a plurality of flash EEPROM cells on a single substrate. Also typically included on the single chip or die substrate are peripheral circuit portions including input/output circuitry for selectively addressing the individual memory cells. During formation of the chip or die, steps are also performed to provide electrical connections or “contacts” for the memory cells. These steps are performed, following formation of the memory cells, to connect the memory cell gate structures, source regions, and drain regions to other parts of the chip. For miniaturization, it is desirable to dispose adjacent gate structures and their contacts as closely together as possible. Unfortunately, these interconnecting conductors must sometimes be positioned farther apart than desirable for the device elements to which they are connected.
Thus, there have been intensive efforts to discover ways, preferably using existing equipment and processes, to achieve improvements in reduced spacing and increased density between and within semiconductor devices. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.